DESIGN AND ANALYSIS OF LOW POWER DUAL EDGE TRIGGERED FLIP FLOP USING MULTI THRESHOLD CMOS
Keywords:SAFF, SETSAFF, DETSAFF, DCDFF, TG, DSPFF, pulse triggered, low power, FF with minimum transistors, MTCMOS
In this work, a low power dual edge triggered flip flop design using multi threshold CMOS is proposed. Multi-threshold CMOS technique is also applied to get low power dissipation. As a result, no. of transistors in pulse-generation circuit has been reduced for power and area saving. Proposed Flip Flop (FF) has two new feature methods. First method, Transmission gate method. Second method, pass transistor method. Various post layout simulation results based on CMOS 90-nm technology reveal that the proposed design features the best power-delay product performance in all FF designs under comparison
I. A. P. Chandrakasan, S. Sheng, and R W. Brodersen, “Low-Power CMOS Digital Design,” IEEE Journal of Solid-State Circuits, vol. 27, no. 4, pp. 473-484, April 1992.
II. H. Kawaguchi and T. Sakurai, “A Reduced Clock-Swing Flip-Flop (RCSFF) for 63% PoweReduction,” IEEE Journal of Solid-State Circuits, vol. 33, no. 5, pp. 807-11, May 1998.
III. A. P. Chandrakasan, W. J. Bowhill, and F. Fox, “High-Performance Microprocessor Circuits,” 1st ed. Piscataway, NJ: IEEE Press,2001.
IV. P. Zhao, J. McNeely, W. Kuang, N. Wang, and Z. Wang, “Design of sequential elements for low power clocking system,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 5, pp. 914918, May 2011.
V. J. Tschanz, S. Narendra, Z. Chen, S. Borkar, M. Sachdev, and V. De,
VI. “Comparative Delay and Energy of Single Edge-Triggered & Dual EdgeTriggered Pulsed Flip-Flops for High-Performance Microprocessors,” ISLPED’01, pp. 147-152, Aug. 2001.
VII. V. Stojanovic and V. Oklobdzija, “Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems,” IEEE J. Solid-State Circuits, vol. 34, no. 4, pp. 536–548, Apr. 1999.
VIII. S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, “1 -V Power Supply High-speed Digital Circuit Technology with Multithreshold-Voltage CMOS,” IEEE Journal of Solid-State Circuits, vol. 30, no. 8, pp. 847-54, Aug. 1995.
IX. P. Zhao, T. Darwish, and M. Bayoumi, “High-performance and lowpower conditional discharge flip-flop ,” IEEE Transaction on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 5, pp. 477-484, May 2004.
X. G. Aliakbar and M. Hamid, "Dual-edge triggered static pulsed flip-flops," 18th IEEE International Conference on VLSI Design, pp. 846-849, Jan. 2005.
XI. N. K. Saini and K. K. Kashyap, “Low Power Dual Edge Triggered FlipFlop,” IEEE International Conference onSignal Propagation and Computer Technology (ICSPCT), pp. 125-128, July 2014.
XII. J.F. Lin, “Low-power pulse-triggered flip-flop design based on a signal feed-through scheme” IEEE Transaction on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 1, pp. 181-185, Jan 2014.
How to Cite
Copyright (c) 2021 International Education and Research Journal (IERJ)
This work is licensed under a Creative Commons Attribution 4.0 International License.