AN 8-BIT PIPELINE ADC IN 65NM WITH 250MHZ NYQUIST FREQUENCY TO OBTAIN 6B ENOB
Keywords:Analog-to-Digital Converter (ADC), Interleaved Sample and Hold Circuit (ISHC), Multiplying DAC (MDAC), high speed, low power
In this paper, an 8-bit Pipeline ADC, with 1V supply at 250MHz Nyquist frequency has been proposed. The ADC architecture uses 1.5bit stages as sub-ADCs for power reduction. This work targets 6b ENOB at both low and high input frequencies (ranging from 1-7MHz). The design has been implemented in 65nm CMOStechnology. Comparative power consumption for 180nm, 90nm and 65nm is obtained which shows a reasonable power reduction of 3.067mW from 180nm to 65nm.
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