DESIGN AND ANALYSIS OF LOW POWER DUAL EDGE TRIGGERED FLIP FLOP USING MULTI THRESHOLD CMOS

Dr.B. Paulchamy, K. Mahendrakan, N. Abimugesh, K. Ajithkumar, M. Gokul, R. Karthick

Abstract


In this work, a low power dual edge triggered flip flop design using multi threshold CMOS is proposed. Multi-threshold CMOS technique is also applied to get low power dissipation. As a result, no. of transistors in pulse-generation circuit has been reduced for power and area saving. Proposed Flip Flop (FF) has two new feature methods. First method, Transmission gate method. Second method, pass transistor method. Various post layout simulation results based on CMOS 90-nm technology reveal that the proposed design features the best power-delay product performance in all FF designs under comparison.  


Keywords


SAFF, SETSAFF, DETSAFF, DCDFF, TG, DSPFF, pulse triggered, low power, FF with minimum transistors, MTCMOS.

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